Digital VLSI Chip Design with Cadence and Synopsys CAD Tools

I wanted to implement a test chip with custom-design standard cell library elements. I wanted to take an RTL design and perform synthesis, backend (place and route), and top-level chip assembly (with other custom components) using a 0.13 um technology and an accompanying standard cell library. My background prior to reading this book was exclusively custom chip design, though I was familiar with HDL coding (for FPGAs).Going through this book allowed me to learn the digital ASIC design flow, and provided enough details for me to figure out how to incorporate my own custom-designed standard cells, which required some hacking and/or modifications to the standard design flow. As you read through this book, there will be plenty of areas of confusion, and the sample scripts will not work without modification to your specific design software setup. However, I gave the book five stars based on the relative value it provides over reading the user manuals of the software tools individually or searching the web.P.S. the test chip worked!

A lot has changed since this was published.

Fantastic text using insight, background material, and overall knowledge from premier user in EDA design tools. Erik does a tremendous job of explaining things and providing step by step detail in using complex VLSI design tools for creating design flows. I have known Erik for several years and he amazes me in his level of compassion, knowledge, and gift of teaching in a very complex area. This book is excellent for users both in the academic and commercial world who are looking for a guide that will help users learn the material well and provides a great reference for those that already have backgrounds in this area. This is a book that belongs on everyone's bookshelf not to mention having it very close by for reference while doing anything of importance in VLSI. More importantly, Erik provides the files for users, so that they can follow along and create their own libraries.

I highly recommend this book for anyone who is setting up Cadence/Synopysys tool flow with the NCSU design kit.I have setup the complete flow (analog, digital, mixed-mode sims., and from laying out std. cells using the template, to synthesis and place and route -- including generating the necessary timing and abstract files) in Cadence using only this book and the scripts provided.ALL scripts can be found online at the book's website. Doing a simple web search of the author's name, UofU, or the book's title will point you to the book's webpage.You should keep in mind the purpose of this book is NOT to teach you about libraries, synthesis, place and route, and other VLSI topics. This book assumes you understand VLSI design flow and concepts.Again, I highly recommend this book for anyone who needs to set up the tool flow.

It is an ideal book for starter to learn the design flow of digital implementation using Cadence and Synopsys platform. The usages of the tools are described (much better than reading the long manuals). However, I think the starters usually cannot do the steps as smoothly as described in the book, since the users usually will encounter some error messages. The book seldom mention the method to solve the error messages displayed by the tools.

Digitial VLSI Chip Design with ~~~ Book's Papers is not good. (likely newspaper's paper)

I have put my purchase on 11-Oct-2010. The expected arrival date is 20-oct-2010. Yet until now I still have not received my item.

This book shares scripts, tool descriptions... And the information to set up tools. I had to set up the Cadence tools for my school and thanks to this book, weeks or maybe months, were saved. There are some differences between the content of this book and the new IC617 and IC618 Cadence design suites but the advice made those setups pretty pain free too. Some changes in tool names and packages that include the tools.